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HT82K96E usb multimedia keyboard encoder 8-bit otp mcu rev. 2.00 1 october 11, 2007 general description this device is an 8-bit high performance risc-like microcontroller designed for usb product applications. it is particularly suitable for use in products such as mice, keyboards and joystick. a halt feature is in- cluded to reduce power consumption. features operating voltage: f sys =6m/12mhz: 4.4v~5.5v low voltage reset function 32 bidirectional i/o lines (max.) 8-bit programmable timer/event counter with over - flow interrupt 16-bit programmable timer/event counter and over - flow interrupts crystal oscillator (6mhz or 12mhz) watchdog timer 6 channels 8-bit a/d converter ps2 and usb modes supported usb 2.0 low speed function 4 endpoints supported (endpoint 0 included) 4096 15 program memory rom 160 8 data memory ram halt function and wake-up feature reduce power consumption 8-level subroutine nesting up to 0.33 s instruction cycle with 12mhz system clock at v dd =5v bit manipulation instruction 15-bit table read instruction 63 powerful instructions all instructions in one or two machine cycles 28-pin sop, 48-pin ssop package technical document tools information faqs application note
block diagram HT82K96E rev. 2.00 2 october 11, 2007

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pin assignment pin description pin name i/o rom code option description pa0~pa5 pa6/tmr0 pa7/tmr1 i/o pull-low pull-high wake-up cmos/nmos/pmos bidirectional 8-bit input/output port. each bit can be configured as a wake-up input by rom code option. the input or output mode is con- trolled by pac (pa control register). pull-high resistor options: pa0~pa7 pull-low resistor options: pa0~pa5 cmos/nmos/pmos options: pa0~pa7 wake up options: pa0~pa7 pa6 and pa7 are pin-shared with tmr0 and tmr1 input, respectively. pa0~pa5 can be used as usb mouse x1, x2, y1, y2, z1, z2 input for mouse hardware wake-up function pa6, pa7 can be used as usb mouse button input for mouse hardware wake-up function pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 pb5/an5 pb6/vrl pb7/vrh i/o pull-high analog input bidirectional 8-bit input/output port. software instructions determine the cmos output or schmitt trigger input with pull-high resistor (determined by pull-high options). the pb can be used as analog input of the analog to digital converter (determined by options). pb6, pb7 can be used as usb mouse button input for mouse hardware wake-up function pd0~pd7 i/o pull-high bidirectional i/o lines. software instructions determine the cmos out - put or schmitt trigger input with pull-high resistor (determined by 1-bit pull-high option). pd4 can be used as usb mouse button input for mouse hardware wake-up function HT82K96E rev. 2.00 3 october 11, 2007 * 8 * . * 1 * 0 * * * 7 * * * 7 9 7 8 7 . 7 1 7 0 7 * 7 7 7 7 7 9 8 . 1 0 7 * 0 1 . 8 9 7 * 0 1 . 8 9 7 *
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pin name i/o rom code option description vss negative power supply, ground pc0~pc7 i/o pull-high bidirectional i/o lines. software instructions determine the cmos out - put or schmitt trigger input with pull-high resistor (determined by pull-high options). pc0 can be used as usb mouse irpt control pin for mouse hardware wake-up function res i schmitt trigger reset input. active low vdd positive power supply v33o o 3.3v regulator output usbd+/clk i/o usbd+ or ps2 clk i/o line usb or ps2 function is controlled by software control register usbd-/data i/o usbd- or ps2 data i/o line usb or ps2 function is controlled by software control register osc1 osc2 i o osc1, osc2 are connected to an 6mhz or 12mhz crystal/resonator (determined by software instructions) for the internal system clock. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature...............................0 cto70 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =6mhz 4.4 5.5 v f sys =12mhz 4.4 5.5 v i dd1 operating current (6mhz crystal) 5v no load, f sys =6mhz 6.5 12 ma i dd2 operating current (12mhz crystal) 5v no load, f sys =12mhz 7.5 16 ma i stb1 standby current (wdt enabled) 5v no load, system halt, usb suspend 250 a i stb2 standby current (wdt disabled) 5v no load, system halt, usb suspend 230 a v il1 input low voltage for i/o ports 5v 0 0.8 v v ih1 input high voltage for i/o ports 5v 2 5v v il2 input low voltage (res )5v 0 0.4v dd v v ih2 input high voltage (res )5v 0.9v dd v dd v i ol1 i/o port sink current for pb, pc1~pc7, pd 5v v ol =3.4v 12 17 ma i ol2 i/o port sink current for pb, pc1~pc7, pd 5v v ol =0.4v 24 ma i ol3 i/o port sink current for pa 5v v ol =0.4v 510 ma HT82K96E rev. 2.00 4 october 11, 2007
symbol parameter test conditions min. typ. max. unit v dd conditions i ol4 i/o port sink current for pc0 5v v ol =0.4v 10 25 ma i oh1 i/o port source current for pc0 5v v oh =3.4v 8 16 ma i oh2 i/o port source current for pa, pb, pc1~pc7, pd 5v v oh =3.4v 2 5 ma r ph pull-high resistance for pa, pb, pc, pd 5v 25 50 80 k r pl pull-low resistance for pa1~pa5 5v 15 30 45 k v lvr low voltage reset 3 3.4 4.0 v v v33o 3.3v regulator output 5v i v33o = 5ma 3.0 3.3 3.6 v e a/d a/d conversion error 5v total error 1 2 lsb a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (crystal osc) 5v 6 12 mhz f timer timer i/p frequency (tmr0/tmr1) 5v 0 12 mhz t wdtosc watchdog oscillator 5v 15 31 70 s t wdt1 watchdog time-out period (wdt osc) 5v without wdt prescaler 4 8 16 ms t wdt2 watchdog time-out period (system clock) without wdt prescaler 1024 t sys t res external reset low pulse width 1 s t sst system start-up timer period wake-up from halt 1024 t sys power-up, watchdog time-out from normal 1024 t wdtosc t int interrupt pulse width 1 s t adc a/d conversion time 64 t a/d note: t a/d = 1 f a/d ,f a/d =a/d clock source frequencies (6mhz, 3mhz, 1.5mhz, 0.75mhz) HT82K96E rev. 2.00 5 october 11, 2007
functional description HT82K96E rev. 2.00 6 october 11, 2007 execution flow the system clock for the microcontroller is derived from either a crystal or an rc oscillator. the system clock is internally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute in a cycle. if an instruction changes the program counter, two cycles are required to complete the instruction. program counter pc the program counter (pc) controls the sequence in which the instructions stored in the program rom are executed and its contents specify a full range of pro - gram memory. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupts, the pc manipulates the program transfer by loading the address corre - sponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed to the next instruction. the lower byte of the program counter (pcl) is a read - able and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within the current program rom page. when a control transfer takes place, an additional dummy cycle is required. 7 * 7 * 7 * : $ ( ( ; < = ( ( ; 6 < : $ ( ( ; 5 < = ( ( ; < : $ ( ( ; 5 < = ( ( ; 5 < 5 5 ! ( , > ( ; ( , < execution flow mode program counter *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 000000000000 usb interrupt 000000000100 timer/event counter 0 overflow 000000001000 timer/event counter 1 overflow 000000001100 skip program counter+2 loading pcl *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *11~*0: program counter bits s11~s0: stack register bits #11~#0: instruction code bits @7~@0: pcl bits
HT82K96E rev. 2.00 7 october 11, 2007 program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 4096 15 bits, addressed by the program counter and ta - ble pointer. certain locations in the program memory are reserved for special usage: location 000h this area is reserved for program initialization. after chip reset, the program always begins execution at lo - cation 000h. location 004h this area is reserved for the usb interrupt service program. if the usb interrupt is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004h. location 008h this area is reserved for the timer/event counter 0 in - terrupt service program. if a timer interrupt results from a timer/event counter 0 overflow, and if the in - terrupt is enabled and the stack is not full, the program begins execution at location 008h . location 00ch this location is reserved for the timer/event counter 1 interrupt service program. if a timer interrupt results from a timer/event counter 1 overflow, and the inter - rupt is enabled and the stack is not full, the program begins execution at location 00ch. table location any location in the program memory can be used as look-up tables. the instructions tabrdc [m] (the current page, one page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). only the desti - nation of the lower-order byte in the table is well-defined, the other bits of the table word are trans - ferred to the lower portion of tblh, and the remaining 1-bit words are read as 0 . the table higher-order byte register (tblh) is read only. the table pointer (tblp) is a read/write register (07h), which indicates the table location. before accessing the table, the lo - cation must be placed in the tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. errors can occur. in other words, using the table read instruction in the main rou- tine and the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt is supposed to be disabled prior to the table read in- struction. it will not be enabled until the tblh has been backed up. all table related instructions require two cycles to complete the operation. these areas may function as normal program memory depending upon the requirements. stack register stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither read - able nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. 0 ( ? ! : : : 2 : : 2
3 ( , @ ( / ( ( ? ) 3 ( ( ( ? ( # > 6 ( ? , ( ; 0 1 ( a " ! < # > 6 ( ? , ( ; 0 1 ( a " ! < b ( ( ! ( % ( ( ( : 2 2 8 2 * 2 2 ) 3 ( ( ( ? ( program memory instruction table location *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *11~*0: table location bits p11~p8: current program counter bits @7~@0: table pointer bits
HT82K96E rev. 2.00 8 october 11, 2007 at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the pro - gram counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. in a similar case, if the stack is full and a call is sub - sequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return ad - dresses are stored). data memory ram for bank 0 the data memory is designed with 190 8 bits. the data memory is divided into two functional groups: spe - cial function registers and general purpose data mem - ory (160 8). most are read/write, but some are read only. the special function registers include the indirect ad - dressing registers (r0;00h, r1;02h), bank register (bp, 04h), timer/event counter 0 ( tmr0 ;0dh), timer/event counter 0 control register (tmr0c;0eh), timer/event counter 1 higher order byte register (tmr1h;0fh), timer/event counter 1 lower order byte register (tmr1l;10h), timer/event counter 1 control register (tmr1c;11h), program counter lower-order byte register (pcl;06h), memory pointer registers (mp0;01h, mp1;03h), accumulator (acc;05h), table pointer (tblp;07h), table higher-order byte register (tblh;08h), status register (status;0ah), interrupt control register (intc;0bh), watchdog timer option setting register (wdts;09h), i/o registers (pa;12h, pb;14h, pc;16h, pd;18h), i/o control registers (pac;13h, pbc;15h, pcc;17h, pdc;19h). usb/ps2 status and control register (usc;1ah), usb endpoint interrupt status register (usr;1bh), system clock con - trol register (scc;1ch). a/d converter status and con - trol register (adsc;1dh) and a/d converter result register (adr;1eh). the remaining space before the 20h is reserved for future expanded usage and reading these locations will get 00h . the general purpose data memory, addressed from 20h to bfh, is used for data and control information under instruction com - mands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di - rectly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through memory pointer registers (mp0 or mp1). & , ( ! (
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HT82K96E rev. 2.00 9 october 11, 2007 data memory ram for bank 1 the special function registers used in usb interface are located in ram bank 1. in order to access bank1 regis - ter, only the indirect addressing pointer mp1 can be used and the bank register bp should set to 1. the map - ping of ram bank 1 is as shown. indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op- eration of [00h] ([02h]) will access data memory pointed to by mp0 (mp1). reading location 00h (02h) itself indi- rectly will return the result 00h. writing indirectly results in no operation. the indirect addressing pointer (mp0) always point to bank0 ram addresses no matter the value of bank register (bp). the indirect addressing pointer (mp1) can access bank0 or bank1 ram data according the value of bp is set to 0 or 1 respectively. the memory pointer registers (mp0 and mp1) are 8-bit registers. accumulator the accumulator is closely related to alu operations. it is also mapped to location 05h of the data memory and can carry out immediate data operations. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera - tions. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the status register. status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addi - tion operations related to the status register may give different results from those intended. bit no. label function 0c c is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a ro - tate through carry instruction. 1ac ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3ov ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6~7 unused bit, read as 0 status (0ah) register " % " d ( ! 3 " % ( % ( = ! + # #
: : : : : : : : 7 * 2 * 2 * 2 * 7 2 * * 2 * 0 2 * 1 2 * . 2 * 8 2 * 9 2 * 2 * / 2 * 2 : : 2 ram bank 1 note: register 45h is defined for version c or later ver - sion
HT82K96E rev. 2.00 10 october 11, 2007 the to flag can be affected only by system power-up, a wdt time-out or executing the clr wdt or halt instruction. the pdf flag can be affected only by ex - ecuting the halt or clr wdt instruction or dur - ing a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe - cuting the subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status are important and if the subroutine can cor - rupt the status register, precautions must be taken to save it properly. interrupt the device provides an external interrupt and internal timer/event counter interrupts. the interrupt control register (intc;0bh) contains the interrupt control bits to set the enable/disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain inter - rupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc may be set to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related in- terrupt is enabled, until the sp is decremented. if immedi- ate service is desired, the stack must be prevented from becoming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro - gram memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the con - tents should be saved in advance. usb interrupts are triggered by the following usb events and the related interrupt request flag (usbf; bit 4 of intc) will be set. the access of the corresponding usb fifo from pc the usb suspend signal from pc the usb resume signal from pc usb reset signal when the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to loca - tion 04h will occur. the interrupt request flag (usbf) and emi bits will be cleared to disable other interrupts. when pc host access the fifo of the HT82K96E, the corresponding request bit of usr is set, and a usb in - terrupt is triggered. so user can easy to decide which fifo is accessed. when the interrupt has been served, the corresponding bit should be cleared by firmware. when HT82K96E receive a usb suspend signal from host pc, the suspend line (bit0 of usc) of the HT82K96E is set and a usb interrupt is also triggered. also when HT82K96E receive a resume signal from host pc, the resume line (bit3 of usc) of HT82K96E is set and a usb interrupt is triggered. whatever there are usb reset signal is detected, the usb interrupt is triggered. the internal timer/event counter 0 interrupt is initial- ized by setting the timer/event counter 0 interrupt re- quest flag (; bit 5 of intc), caused by a timer 0 overflow. when the interrupt is enabled, the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related interrupt request flag (t0f) will be re- set and the emi bit cleared to disable further interrupts. the internal timer/even counter 1 interrupt is initialized by setting the timer/event counter 1 interrupt request flag (;bit 6 of intc), caused by a timer 1 overflow. when the interrupt is enabled, the stack is not full and the t1f is set, a subroutine call to location 0ch will occur. the related interrupt request flag (t1f) will be reset and the emi bit cleared to disable further interrupts. bit no. label function 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 eui controls the usb interrupt (1= enabled; 0= disabled) 2 et0i controls the timer/event counter 0 interrupt (1= enabled; 0= disabled) 3 et1i controls the timer/event counter 1 interrupt (1= enabled; 0= disabled) 4 usbf usb interrupt request flag (1= active; 0= inactive) 5 t0f internal timer/event counter 0 request flag (1= active; 0= inactive) 6 t1f internal timer/event counter 1 request flag (1= active; 0= inactive) 7 unused bit, read as 0 intc (0bh) register
HT82K96E rev. 2.00 11 october 11, 2007 during the execution of an interrupt subroutine, other in - terrupt acknowledge signals are held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to enable an in - terrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. no. interrupt source priority vector a usb interrupt 1 04h b timer/event counter 0 overflow 2 08h c timer/event counter 1 overflow 3 0ch the timer/event counter 0/1 interrupt request flag (t0f/t1f), usb interrupt request flag (usbf), enable timer/event counter 0/1 interrupt bit (et0i/et1i), en - able usb interrupt bit (eui) and enable master interrupt bit (emi) constitute an interrupt control register (intc) which is located at 0bh in the data memory. emi, eui, et0i and et1i are used to control the enabling/dis- abling of interrupts. these bits prevent the requested in- terrupt from being serviced. once the interrupt request flags (t0f, t1f, usbf) are set, they will remain in the intc register until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the call subroutine within the interrupt subroutine. in- terrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well con trolled, the original control sequence will be dam - aged once the call operates in the interrupt subrou - tine. oscillator configuration there is an oscillator circuits in the microcontroller. this oscillator is designed for system clocks. the halt mode stops the system oscillator and ignores an exter - nal signal to conserve power. a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator. no other external components are required. in stead of a crystal, a resonator can also be connected between osc1 and osc2 to get a frequency reference, but two external capacitors in osc1 and osc2 are required. the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. even if the system enters the power down mode, the system clock is stopped, but the wdt oscillator still works within a period of approximately 31 s. the wdt oscillator can be disabled by rom code option to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator), or instruction clock (sys- tem clock divided by 4), determines the rom code op- tion. this timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the watchdog timer can be disabled by rom code option. if the watchdog timer is disabled, all the executions related to the wdt result in no operation. ! ( , > ) * 8 6 ? ( + ( ! , . 6 ? ( 8 6 6 (
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HT82K96E rev. 2.00 12 october 11, 2007 once the internal wdt oscillator (rc oscillator with a period of 31 s/5v normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of 8ms/5v. this time-out period may vary with tempera - tures, vdd and process variations. by invoking the wdt prescaler, longer time-out periods can be realized. writing data to ws2, ws1, ws0 (bit 2,1,0 of the wdts) can give different time-out periods. if ws2, ws1, and ws0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 1s/5v. if the wdt oscillator is disabled, the wdt clock may still come from the instruc - tion clock and operates in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the logic can only be restarted by external logic. the high nibble and bit 3 of the wdts are reserved for user s defined flags, which can only be set to 10000 (wdts.7~wdts.3). if the device operates in a noisy environment, using the on-chip 32khz rc oscillator (wdt osc) is strongly rec - ommended, since the halt will stop the system clock. ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 wdts (09h) register the wdt overflow under normal operation will initialize chip reset and set the status bit to . but in the halt mode, the overflow will initialize a warm reset and only the program counter and sp are reset to zero. to clear the contents of wdt (including the wdt prescaler), three methods are adopted; external reset (a low level to res ), software instruction and a halt instruction. the software instruction include clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruction, only one can be active depend - ing on the rom code option clr wdt times selec - tion option .ifthe clr wdt is selected (i.e. clrwdt times equal one), any execution of the clr wdt in - struction will clear the wdt. in the case that clr wdt and clr wdt are chosen (i.e. clrwdt times equal two), these two instructions must be executed to clear the wdt; otherwise, the wdt may reset the chip as a result of time-out. the time-out periods defined in wdts can used as wake-up period in the mouse hardware wake-up func - tion. please reference to mouse hardware wake-up function description. power down operation halt the halt mode is initialized by the halt instruction and results in the following... the system oscillator will be turned off but the wdt oscillator remains running (if the wdt oscillator is se - lected). the contents of the on chip ram and registers remain unchanged. wdt and wdt prescaler will be cleared and re - counted again (if the wdt clock is from the wdt os - cillator). all of the i/o ports maintain their original status. the pdf flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig - nal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow per - forms a warm reset . after the to and pdf flags are examined, the reason for chip reset can be determined. the pdf flag is cleared by system power-up or execut - ing the clr wdt instruction and is set when execut - ing the halt instruction. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and sp; the others remain in their original status. the port a wake-up and interrupt methods can be con- sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by mask option. awakening from an i/o port stim- ulus, the program will resume execution of the next in- struction. if it awakens from an interrupt, two sequence may occur. if the related interrupt is disabled or the inter- rupt is enabled but the stack is full, the program will re- sume execution at the next instruction. if the interrupt is enabled and the stack is not full, the regular interrupt re - sponse takes place. if an interrupt request flag is set to 1 before entering the halt mode, the wake-up func - tion of the related interrupt will be disabled. once a wake-up event occurs, it takes 1024 t sys (system clock period) to resume normal operation. in other words, a dummy period will be inserted after a wake-up. if the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation
HT82K96E rev. 2.00 13 october 11, 2007 the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm re - set that resets only the program counter and sp, leav - ing the other circuits in their original state. some regis - ters remain unchanged during other reset conditions. most registers are reset to the initial condition when the reset conditions are met. by examining the pdf and to flags, the program can distinguish between different chip resets . to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys - tem reset (power-up, wdt time-out or res reset) or the system awakes from the halt state. when a system reset occurs, the sst delay is added during the reset period. any wake-up from halt will en- able the sst delay. the functional unit chip reset status are shown below. program counter 000h interrupt disable prescaler clear wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack reset circuit + ( ! + 2 # , " ! ! ( ! 6 ? ( , reset configuration ( 6 $ ( ( ! reset timing chart
HT82K96E rev. 2.00 14 october 11, 2007 the states of the registers is summarized in the table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) tmr0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu 00-0 1000 00-0 1000 tmr1h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- 00-0 1--- 00-0 1--- program counter 000h 000h 000h 000h 000h 000h 000h mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu --uu uuuu --01 uuuu intc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 wdts 1000 0111 1000 0111 1000 0111 1000 0111 uuuu uuuu 1000 0111 1000 0111 pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 awr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pipe 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 stall 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 misc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 fifo0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo3 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 usc 11xx 0000 uuxx uuuu 11xx 0000 11xx 0000 uuxx uuuu uu00 0u00 uu00 0u00 usr 0100 0000 uuuu uuuu 0100 0000 0100 0000 uuuu uuuu 01uu 0000 01uu 0000 scc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0u00 u000 0u00 u000 adsc 1000 0000 uuuu uuuu 1000 0000 1000 0000 uuuu uuuu 1000 0000 1000 0000 adr xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx note: * stands for warm reset u stands for unchanged x stands for unknown
HT82K96E rev. 2.00 15 october 11, 2007 bit no. label function 0~2, 5 unused bit, read as 0 3te to define the tmr0 active edge of timer/event counter 0 (0=active on low to high; 1=active on high to low) 4 ton to enable/disable timer 0 counting (0=disabled; 1=enabled) 6 7 tm0 tm1 to define the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr0c (0eh) register bit no. label function 0~2, 5 unused bit, read as 0 3te to define the tmr1 active edge of timer/event counter 1 (0=active on low to high; 1=active on high to low) 4 ton to enable/disable timer 1 counting (0=disabled; 1=enabled) 6 7 tm0 tm1 to define the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr1c (11h) register timer/event counter two timer/event counters (tmr0, tmr1) are imple - mented in the microcontroller. the timer/event counter 0 contains an 8-bit programmable count-up counter and the clock may comes from an external source or from f sys /4. the timer/event counter 1 contains an 16-bit program - mable count-up counter and the clock may come from an external source or from the system clock divided by 4.

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HT82K96E rev. 2.00 16 october 11, 2007 using the internal clock source, there is only 1 reference time-base for timer/event counter 0. the internal clock source is coming from f sys /4. the external clock input allows the user to count exter - nal events, measure time intervals or pulse widths. using the internal clock source, there is only 1 reference time-base for timer/event counter 1. the internal clock source is coming from f sys /4. the external clock input allows the user to count external events, measure time intervals or pulse widths. there are 2 registers related to the timer/event counter 0; tmr0 ([0dh]), tmr0c ([0eh]). two physical regis - ters are mapped to tmr0 location; writing tmr0 makes the starting value be placed in the timer/event counter 0 preload register and reading tmr0 gets the contents of the timer/event counter 0. the tmr0c is a timer/event counter control register, which defines some options. there are 3 registers related to timer/event counter 1; tmr1h (0fh), tmr1l (10h), tmr1c (11h). writing tmr1l will only put the written data to an internal lower-order byte buffer (8 bits) and writing tmr1h will transfer the specified data and the contents of the lower-order byte buffer to tmr1h and tmr1l preload registers, respectively. the timer/event counter 1 preload register is changed by each writing tmr1h op- erations. reading tmr1h will latch the contents of tmr1h and tmr1l counters to the destination and the lower-order byte buffer, respectively. reading the tmr1l will read the contents of the lower-order byte buffer. the tmr1c is the timer/event counter 1 control register, which defines the operating mode, counting en- able or disable and active edge. the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from an external (tmr0/tmr1) pin. the timer mode functions as a nor - mal timer with the clock source coming from the f sys /4 (timer0/timer1). the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr0/tmr1). the counting is based on the f sys /4 (timer0/timer1). in the event count or timer mode, once the timer/event counter 0/1 starts counting, it will count from the current contents in the timer/event counter 0/1 to ffh or ffffh. once overflow occurs, the counter is reloaded from the timer/event counter 0/1 preload register and generates the interrupt request flag (t0f/t1f; bit 5/6 of intc) at the same time. in the pulse width measurement mode with the ton and te bits equal to one, once the tmr0/tmr1 has re - ceived a transient from low to high (or high to low if the te bits is 0 ) it will start counting until the tmr0/tmr1 returns to the original level and resets the ton. the measured result will remain in the timer/event counter 0/1 even if the activated transient occurs again. in other words, only one cycle measurement can be done. until setting the ton, the cycle measurement will function again as long as it receives further transient pulse. note that, in this operating mode, the timer/event counter 0/1 starts counting not according to the logic level but according to the transient edges. in the case of counter overflows, the counter 0/1 is reloaded from the timer/event counter 0/1 preload register and issues the interrupt request just like the other two modes. to en - able the counting operation, the timer on bit (ton; bit 4 of tmr0c/tmr1c) should be set to 1. in the pulse width measurement mode, the ton will be cleared automati - cally after the measurement cycle is completed. but in the other two modes the ton can only be reset by in- structions. the overflow of the timer/event counter 0/1 is one of the wake-up sources. no matter what the oper- ation mode is, writing a 0 to et0i/et1i can disable the corresponding interrupt services. in the case of timer/event counter 0/1 off condition, writing data to the timer/event counter 0/1 preload reg- ister will also reload that data to the timer/event coun- ter 0/1. but if the timer/event counter 0/1 is turned on, data written to it will only be kept in the timer/event counter 0/1 preload register. the timer/event counter 0/1 will still operate until overflow occurs (a timer/event counter 0/1 reloading will occur at the same time). when the timer/event counter 0/1 (reading tmr0/tmr1) is read, the clock will be blocked to avoid errors. as clock blocking may results in a counting error, this must be taken into consideration by the program - mer.
HT82K96E rev. 2.00 17 october 11, 2007 input/output ports there are 32 bidirectional input/output lines in the microcontroller, labeled from pa to pd, which are mapped to the data memory of [12h], [14h], [16h] and [18h] respectively. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instru ction mov a,[m] (m=12h, 14h, 16h or 18h). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc, pdc) to control the input/output configuration. with this control register, cmos/nmos/pmos output or schmitt trigger input with or without pull-high/low re - sistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. to function as an in - put, the corresponding latch of the control register must write 1 . the input source also depends on the control register. if the control register bit is 1 , the input will read the pad state. if the control register bit is 0 , the contents of the latches will move to the internal bus. the latter is possible in the read-modify-write instruction. for output function, cmos/nmos/pmos configura - tions can be selected (nmos and pmos are available for pa only). these control registers are mapped to loca- tions 13h, 15h, 17h and 19h. after a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high/low options). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h, 16h or 18h) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. there are pull-high/low (pa only) options available for i/o lines. once the pull-high/low option of an i/o line is selected, the i/o line have pull-high/low resistor. other - wise, the pull-high/low resistor is absent. it should be noted that a non-pull-high/low i/o line operating in input mode will cause a floating state. it is recommended that unused or not bonded out i/o lines should be set as output pins by software instruction to avoid consuming power under input floating state. - 0 d ( 1 )
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HT82K96E rev. 2.00 18 october 11, 2007 low voltage reset lvr the microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr such as changing a battery, the lvr will au - tomatically reset the device internally. the lvr includes the following specifications: the low voltage (0.9v~v lvr ) has to remain in their original state to exceed 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and do not perform a reset function. the lvr uses the or function with the external res signal to perform chip reset. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip opera - tion at 4mhz system clock. 0 4 0 7 4 7 7 4 4 9 # 0 4 0 0 4 0 # 4 9 ! ( , ! f f , ( ! # ( ( , low voltage reset note: *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the reset mode. mouse hardware wake-up function when the HT82K96E is used for usb mouse application, in order to decrease the power consumption of the HT82K96E in suspend mode. the HT82K96E has built-in mouse hardware wake-up function. once the HT82K96E jump to suspend mode, and the hwkupsb (bit7 of scc) is set to 1. the HT82K96E will automatically switch the irpt control pin (pc0) and detect movement of the x1, x2, y1, y2, z1, z2, corresponding to (pa0~pa5) and the state of the five button corresponding to pa6, pa7, pb6, pb7, and pd4. once there are mouse movement or state change. the HT82K96E will wake-up the mcu by i/o method, otherwise the mcu is in suspend mode. how long the HT82K96E to turn on the irpt, and the low pulse period of the pc0 is defined by bit0~3 of the wdts (wake-up period) and the bit0~bit2 of the scc (led_on period) respectively. the following diagram show the irpt control pin timing. + > 6 ( " ( # g ( "
HT82K96E rev. 2.00 19 october 11, 2007 suspend wake-up remote wake-up if there is no signal on usb bus is over 3ms, the HT82K96E will go into suspend mode . the suspend line (bit 0 of usc) will be set to 1 and a usb interrupt is triggered to indicate the HT82K96E should jump to sus - pend state to meet the 500 a usb suspend current spec. in order to meet the 500 a suspend current, the firm - ware should disable the usb clock by clear the usbcken (bit3 of the scc) to 0 . the suspend cur - rent is about 400 a. also the user can further decrease the suspend current to 250 a by set the susp2 (bit4 of the scc). but if the susp2 is set, the user make sure cannot enable the lvr opt option, otherwise the HT82K96E will be reset. when the resume signal is sent out by the host, the HT82K96E will wake up the mcu by usb interrupt and the resume line (bit 3 of usc) is set. in order to make HT82K96E work properly, the firmware must set the usbcken (bit 3 of scc) to 1 and clear the susp2 (bit4 of the scc). since the resume signal will be cleared before the idle signal is sent out by the host and the sus - pend line (bit 0 of usc) is going to 0 . so when the mcu is detecting the suspend line (bit0 of usc), the resume line should be remembered and taken into con- sideration. after finishing the resume signal, the suspend line will go inactive and a usb interrupt is triggered. the follow- ing is the timing diagram the device with remote wake up function can wake-up the usb host by sending a wake-up pulse through rmwk (bit 1 of usc). once the usb host receive the wake-up signal from HT82K96E. it will send a resume signal to device. the timing as follow: to configure the HT82K96E as ps2 device the HT82K96E can be define as usb interface or ps2 interface by configuring the sps2 (bit 4 of usr) and susb (bit 5 of usr). if sps2=1, and susb=0, the HT82K96E is defined as ps2 interface, pin usbd- is now defined as ps2 data pin and usbd+ is now de - fined as ps2 clk pin. the user can easy to read or write the ps2 data or ps2 clk pin by accessing the corre - sponding bit ps2dai (bit 4 of usc), ps2cki (bit 5 of usc), ps2dao (bit 6 of usc) and s2cko (bit 7 of usc) respectively. the user should make sure that in order to read the data properly, the corresponding output bit must set to 1. for example, if it want to read ps2 data by reading ps2dai, the ps2dao should set to 1. otherwise it always read 0. if sps2=0, and susb=1, the HT82K96E is defined as usb interface. both the usbd- and usbd+ is driving by sie of the HT82K96E. the user only write or read the usb data through the corresponding fifo. both sps2 and susb is default 0 . to configure the adc block the HT82K96E has built-in a 8-bit a/d converter with 6 channels (pb0~pb5). in order to make the a/d con - verter more flexibility, there are two mode: external ref - erence voltage and internal reference voltage. it can easy to configure by setting the adref (bit 6 of usr). for external reference voltage, the reference voltage of the a/d converter comes from external pb6/vrl and pb7/vrh pins. otherwise, the reference voltage is coming from the vdd and vss of mcu. pb0~pb5 is the 6-channels input of the a/d converter, it can easy to define which channel is converting by con- figuring acs2~acs0 (bit 2~0 of adsc). also there are four converter clock source to be selected by setting adcs1 (bit 4 of adsc), adcs0 ( bit 3 of adsc). once the adon (bit 6 of adsc) is set and send the start pulse through start (bit 5 of adsc). the a/d con - verter will be in operation. there are eocb (bit 7 of adsc) to indicate whether the a/d converter is busy or not. the eocb is clear when the conversion is com - pleted. the user can read the converter data by reading the register adr. in order to meet 500ua suspend cur - rent spec. . the user should disable the a/d by clearing adon before jump to suspend mode. / ( ! ( , / g / ( ! ( , / g
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HT82K96E rev. 2.00 20 october 11, 2007 the following is a/d converter timing diagrams usb interface and a/d converter there are 7 registers, including awr (address + remote wake up; 42h in bank 1), stall (43h in bank 1), pipe (44h in bank 1), misc (46h in bank 1), fifo0 (48h in bank 1), fifo1 (49h in bank 1), fifo2 (4ah in bank 1) and fifo3 (4bh in bank 1) used for the usb function. awr register contains current address and a remote wake up function control bit. the initial value of awr is 00h . the address value extracted from the usb command has not to be loaded into this register until the setup stage being finished. bit no. label r/w function 0 wken w remote wake-up enable/disable 7~1 ad6~ad0 w usb device address awr (42h) register pipe register represents whether the corresponding endpoint is accessed by host or not. this register is set only after the time when host accesses the corresponding endpoint. only the last accessed endpoint is shown in this register. stall register shows whether the corresponding endpoint works properly or not. as soon as the endpoint works im- properly, the related bit in the stall has to be set to 1 . the stall will be cleared by usb reset signal. bit no. label r/w function 0 stl0 w stall the endpoint 0 1 stl1 w stall the endpoint 1 2 stl2 w stall the endpoint 2 3 stl3 w stall the endpoint 3 7~4 w unused bit, read as 0 stall (43h) register bit no. label r/w function 0 ep0rw r endpoint 0 accessed 1 ep1rw r endpoint 1 accessed 2 ep2rw r endpoint 2 accessed 3 ep3rw r endpoint 3 accessed 7~4 r unused bit, read as 0 pipe (44h) register , (
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HT82K96E rev. 2.00 21 october 11, 2007 sies. register (for version c or later version) is used to indicate the present signal state which the sie receives and also defines whether the sie has to change the device address automatically. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 func. reserved bit f0_err adr_set r/w r/w r/w reg_adr 01000101b note: bit7 must be 0 func. name r/w description r/w this bit is used to configure the sie to automatically change the device address with the value of the address+remote_wakeup register (42h). when this bit is set to 1 by f/w, the sie will update the device address with the value of the address+remote_wakeup register (42h) after the pc host has successfully read the data from the device by the in operation. the sie will clear the bit after updat - ing the device address. otherwise, when this bit is cleared to 0 , the sie will update the device address immediately after an address is written to the address+re - mote_wakeup register (42h) default 0 f0_err r/w this bit is used to indicate that some errors have occurred when accessing the fifo0. this bit is set by sie and cleared by f/w. default 0 sies (45h) register table misc register combines a command and status to control desired endpoint fifo action and to show the status of wanted endpoint fifo. the misc will be cleared by usb reset signal. bit no. label r/w function 0 req r/w after setting other status of desired one in the misc, endpoint fifo can be requested by setting this bit to 1 . after job has been done, this bit has to be cleared to 0 1 tx r/w this bit defines the direction of data transferring between mcu and endpoint fifo. when the tx is set to 1 , this means that mcu wants to write data to endpoint fifo. after the job has been done, this bit has to be cleared to 0 before terminating re- quest to represent end of transferring. for reading action, this bit has to be cleared to 0 to represent that mcu wants to read data from endpoint fifo and has to be set to 1 after the job done. 2 clear r/w clear the requested endpoint fifo, even the endpoint fifo is not ready. 4 3 selp1 selp0 r/w to define which endpoint fifo is selected, selp1,selp0: 00: endpoint fifo0 01: endpoint fifo1 10: endpoint fifo2 11: endpoint fifo3 5 scmd r/w it is used to show that the data in endpoint fifo is setup command. this bit has to be cleared by firmware. that is to say, even the mcu is busing, the device will not miss any setup commands from host. 6 ready r read only status bit, this bit is used to indicate that the desired endpoint fifo is ready to work. 7 len0 r/w it is used to indicate that a 0-sized packet is sent from host to mcu. this bit should be cleared by firmware. misc (46h) register
HT82K96E rev. 2.00 22 october 11, 2007 mcu can communicate with endpoint fifo by setting the corresponding registers, of which address is listed in the fol - lowing table. after reading current data, next data will show on after 2 s. using to check endpoint fifo status and re - sponse to misc register, if read/write action is still going on. registers r/w bank address bit7~bit0 fifo0 r/w 1 48h data7~data0 fifo1 r/w 1 49h data7~data0 fifo2 r/w 1 4ah data7~data0 fifo3 r/w 1 4bh data7~data0 there are some timing constrains and usages illustrated here. by setting the misc register, mcu can perform reading, writing and clearing actions. there are some examples shown in the following table for endpoint fifo reading, writing and clearing. actions misc setting flow and status read fifo0 sequence 00h
01h
delay 2 s, check 41h
read* from fifo0 register and check not ready (01h)
03h
02h write fifo1 sequence 0ah
0bh
delay 2 s, check 4bh
write* to fifo1 register and check not ready (0bh)
09h
08h check whether fifo0 can be read or not 00h
01h
delay 2 s, check 41h (ready) or 01h (not ready)
00h check whether fifo1 can be written or not 0ah
0bh
delay 2 s, check 4bh (ready) or 0bh (not ready)
0ah read 0-sized packet sequence form fifo0 00h
01h
delay 2 s, check 81h
read once (01h)
03h
02h write 0-sized packet sequence to fifo1 0ah
0bh
delay 2 s, check 0bh
0fh
0dh
08h note: *: there are 2 s existing between 2 reading action or between 2 writing action the definitions of the usb/ps2 status and control register (usc; 1ah) are as shown. bit no. label r/w function 0 susp r read only, usb suspend indication. when this bit is set to 1 (set by sie), it indi- cates the usb bus enters suspend mode. the usb interrupt is also triggered on any changing of this bit. 1 rmwk w usb remote wake up command. it is set by mcu to force the usb host leaving the suspend mode. when this bit is set to 1 ,2 s delay for clearing this bit to 0 is needed to insure the rmwk command is accepted by sie. 2 urst r/w usb reset indication. this bit is set/cleared by usb sie. this bit is used to detect which bus (ps2 or usb) is attached. when the urst is set to 1 , this indicates a usb reset is occurred (the attached bus is usb) and a usb interrupt will be initial - ized. 3 resume r usb resume indication. when the usb leaves suspend mode, this bit is set to 1 (set by sie). this bit will appear 20ms waiting for mcu to detect. when the resume is set by sie, an interrupt will be generated to wake-up the mcu. in order to detecting the suspend state, mcu should set usbcken and clear susp2 (in scc register) to enable the sie detecting function. the resume will be cleared while the susp is going 0 . when mcu is detecting the susp, the resume (causes mcu to wake-up) should be remembered and taken into consideration. 4 ps2dai r read only, usbd-/data input 5 ps2cki r read only, usbd+/clk input 6 ps2dao w data for driving usbd-/data pin when work under 3d ps2 mouse function. (default= 1 ) 7 ps2cko w data for driving usbd+/clk pin when work under 3d ps2 mouse function. (default= 1 ) usc (1ah) register
HT82K96E rev. 2.00 23 october 11, 2007 the usr (usb endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select serial bus (ps2 or usb) and a/d converter operation modes. the endpoint request flags (ep0if, ep1if, ep2if and ep3if) are used to indicate which endpoints are accessed. if an endpoint is accessed, the related endpoint request flag will be set to 1 and the usb interrupt will occur (if usb interrupt is enabled and the stack is not full). when the ac - tive endpoint request flag is served, the endpoint request flag has to be cleared to 0 . bit no. label r/w function 0 ep0if r/w when this bit is set to 1 (set by sie), it indicates the endpoint 0 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 1 ep1if r/w when this bit is set to 1 (set by sie), it indicates the endpoint 1 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 2 ep2if r/w when this bit is set to 1 (set by sie), it indicates the endpoint 2 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 3 ep3if r/w when this bit is set to 1 (set by sie), it indicates the endpoint 3 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 4 sps2 r/w the ps2 function is selected when this bit is set to 1 . (default= 0 ) 5 susb r/w the usb function is selected when this bit is set to 1 . (default= 0 ) 6 adref r/w the reference voltage of a/d converter is coming from the vdd and vss of mcu when this bit is set 1 . otherwise, the reference voltage of a/d converter comes from external pb6/vrl and pb7/vrh pins. (default= 1 ) 7 fifo-cntl w for ice only, 0 for fifo read (default= 0 ); 1 for fifo write usr (1bh) register there is a system clock control register implemented to select the clock used in the mcu. this register consists of usb clock control bit (usbcken), second suspend mode control bit (susp2) and system clock selection (sysclk). bit no. label r/w function 2~0 led_on period r/w to define low pulse period of irpt (pc0) for mouse hardware function. the time base is 31.25 s (1/32khz). default value is 000. 000: 2 base 001: 3 base 010: 5 base 011: 9 base 100: 17 base 101: 33 base 110: 65 base 111: 127 base 3 usbcken r/w usb clock control bit. when this bit is set to 1 , it indicates that the usb clock is enabled. otherwise, the usb clock is turned-off. (default= 0 ) 4 susp2 r/w this bit is used for decreasing power consumption in suspend mode. in normal mode clean this bit=0 (default= 0 ) in halt mode set this bit=1 for decreasing power consumption. 5 r/w undefined, should be cleared to 0 6 sysclk r/w this bit is used to specify the system oscillator frequency used by mcu. if a 6mhz crystal oscillator or resonator is used, this bit should be set to 1 .ifa 12mhz crystal oscillator or resonator is used, this bit should be cleared to 0 (de - fault). 7 hwkupsb r/w hardware halt mode wake-up detect circuit active under power down mode. low active. 0 : wdt timer overflow will wake-up mcu system 1 : wdt timer overflow will start hardware wake-up detect circuit but not wake-up mcu system. scc (1ch) register
HT82K96E rev. 2.00 24 october 11, 2007 the a/d converter implemented in the mcu is a 6-channel 8-bit a/d converter. the reference voltage (high reference voltage and low reference voltage) can be selected as coming from external pins (pb6/vrl and pb7/vrh) or internal power supplies of mcu (vdd and vss). the vrl and vrh are used to set the minimal and maximal boundaries of the full-scale range of the a/d converter. if an analog inputs, vrl or vrh is not used for a/d conversion, it also can be used as a general purpose i/o line. the adsc (a/d converter status and control register) register is used to set the configu - rations and a/d clock sources of a/d converter and control the operation of a/d converter. bit no. label function 2~0 acs2~acs0 these 3 bits are use to select one of eight a/d converter channels for the conversion. the a/d converter input channels an0~an5 are pin-shared with pb0~pb5. pb6/vrl and pb7/vrh are used for the a/d converter reference inputs. acs2,acs1,acs0 : 000/001/010/011/100/101/110/111: an0/an1/an2/an3/an4/an5/vrl/vrh 4 3 adcs1 adcs0 a/d converter clock source selection. adcs1,adcs0: 00: 6mhz 01: 3mhz 10: 1.5mhz 11: 0.75mhz 5 start start the a/d conversion. (0
1
0: start, 0
1: reset a/d converter and a/d data regis - ter) 6 adon this bit is used to control the enable/disable of a/d converter circuit. if this bit is set to 1 the a/d converter enters operating mode. otherwise, the a/d converter will be turned-off 7 eocb end of a/d conversion indication. (0: end of a/d conversion) adsc (1dh) register the a/d converter data register is used to store the result of a/d conversion. bit no. label function 7~0 d7~d0 result of a/d conversion adr (1eh) register mask options the following table shows all kinds of mask option in the microcontroller. all of the mask options must be defined to en- sure proper system functioning. no. option 1 chip lock bit (by bit) 2 pa0~pa7 pull-high resistor enabled or disabled (by bit) 3 pa0~pa5 pull down resistor enabled or disabled (by bit) 4 pb0~pb7 pull-high resistor enabled or disabled (by nibble) 5 pc0~pc7 pull-high resistor enabled or disabled (by nibble) 6 pd0~pd7 pull-high resistor enabled or disabled (by nibble) 7 lvr enable or disable 8 wdt enable or disable 9 wdt clock source: f sys /4 or wdtosc 10 clrwdt instruction(s): 1 or 2 11 pa0~pa7 output structures: cmos/nmos open-drain/pmos open-drain (by bit) 12 pa0~pa7 wake-up enabled or disabled (by bit) 13 a/d converter enabled or disabled
application circuits crystal or ceramic resonator for multiple i/o applications note: the resistance and capacitance for reset circuit should be designed in such a way as to ensure that the vdd is stable and remains within a valid operating voltage range before bringing res to high. x1 can use 6mhz or 12mhz, x1 as close osc1 & osc2 as possible components with * are used for emc issue. components with ** are used for resonator only. components with *** are used for 12mhz application. HT82K96E rev. 2.00 25 october 11, 2007 / 5 ) # / 6 ) 7 7 4 0 > 4 : > : 7 7 / 6 / 5 7 7 7 7 - . / - / . - . - . 4 : * . : f * . : f f f f 4 : : : 4 : > 0 4 : f f 0 f f f * . : f * . : f f f f f
f f f
HT82K96E rev. 2.00 26 october 11, 2007 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
HT82K96E rev. 2.00 27 october 11, 2007 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
HT82K96E rev. 2.00 28 october 11, 2007 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z HT82K96E rev. 2.00 29 october 11, 2007
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf HT82K96E rev. 2.00 30 october 11, 2007
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf HT82K96E rev. 2.00 31 october 11, 2007
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z HT82K96E rev. 2.00 32 october 11, 2007
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none HT82K96E rev. 2.00 33 october 11, 2007
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c HT82K96E rev. 2.00 34 october 11, 2007
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none HT82K96E rev. 2.00 35 october 11, 2007
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c HT82K96E rev. 2.00 36 october 11, 2007
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none HT82K96E rev. 2.00 37 october 11, 2007
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z HT82K96E rev. 2.00 38 october 11, 2007
package information 28-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 697 713 d92 104 e 50 f4 g32 38 h4 12 0 10 HT82K96E rev. 2.00 39 october 11, 2007 8 0 * / : h & 2
48-pin ssop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 395 420 b 291 299 c8 12 c 613 637 d85 99 e 25 f4 10 g25 35 h4 12 0 8 HT82K96E rev. 2.00 40 october 11, 2007 * 8 0 * / : h & 2
product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330 1 b reel inner diameter 62 1.5 c spindle hole diameter 13+0.5 0.2 d key slit width 2 0.5 t1 space between flange 24.8+0.3 0.2 t2 reel thickness 30.2 0.2 ssop 48w symbol description dimensions in mm a reel outer diameter 330 1 b reel inner diameter 100 0.1 c spindle hole diameter 13+0.5 0.2 d key slit width 2 0.5 t1 space between flange 32.2+0.3 0.2 t2 reel thickness 38.2 0.2 HT82K96E rev. 2.00 41 october 11, 2007 /
carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24 0.3 p cavity pitch 12 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4 0.1 p1 cavity to perforation (length direction) 2 0.1 a0 cavity length 10.85 0.1 b0 cavity width 18.34 0.1 k0 cavity depth 2.97 0.1 t carrier tape thickness 0.35 0.01 c cover tape width 21.3 HT82K96E rev. 2.00 42 october 11, 2007 + : /
ssop 48w symbol description dimensions in mm w carrier tape width 32 0.3 p cavity pitch 16 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 14.2 0.1 d perforation diameter 2 min. d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4 0.1 p1 cavity to perforation (length direction) 2 0.1 a0 cavity length 12 0.1 b0 cavity width 16.2 0.1 k1 cavity depth 2.4 0.1 k2 cavity depth 3.2 0.1 t carrier tape thickness 0.35 0.05 c cover tape width 25.5 HT82K96E rev. 2.00 43 october 11, 2007 : / +
HT82K96E rev. 2.00 44 october 11, 2007 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 86-21-6485-5560 fax: 86-21-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5/f, unit a, productivity building, cross of science m 3rd road and gaoxin m 2nd road, science park, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2007 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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